Solid-state drives (SSD) are a form of data storage that use a solid-state memory to store data. Examples of solid state memory include static random access memory (SRAM), dynamic random access memory (DRAM), and flash memory. Unlike conventional disk drives that include several moving components, an SSD does not have moving parts as data are stored electronically and not on a rotating disk. As a result, SSDs experience fewer mechanical failures as they do not include as many moving parts as conventional hard disk drives. SSDs typically have faster startup times compared to conventional hard disk drives as SSDs do not require time for a disk to spin up to a particular speed in order for data to be written to, or read from, the disk.
An SSD may include a plurality of NAND flash memory cells or DRAM memory cells. NAND flash memory may be implemented using single-level cells (SLCs) or multi-level cells (MLCs). SLC flash memory stores a single bit of data per cell, and MLC flash memory stores two or more bits of data per cell. Accordingly, MLC flash has a higher density than that of SLC flash and is more commonly used in an SSD than SLC flash due to its lower price and higher capacity. However, SLC flash typically has a lower bit error rate (BER) making it more reliable than its more complex MLC counterpart.
One drawback of flash memory is that it has a finite number of erase-write cycles regardless of whether it is implemented as SLC or MLC. Wear-leveling operations are typically implemented to prolong the life of the flash memory by spreading out the write operations among the flash units of a flash group so that one flash unit is not constantly being written to and erased. These wear-leveling operations, along with bad block management, error correction, and the coordination of read and write cycles, are typically performed or managed by a single flash controller. However, these conventional flash controllers provide slow read and write times.
Another drawback of SSDs is that they are susceptible to having high bad block rates. FIG. 6A is a block diagram of a conventional SSD having channels 0-n and m bad memory blocks. Each of the channels of memory are bundled together as all of the memory channels are managed by a single memory controller. The bad block rate (“BBR”) of a memory channel of the SSD is determined by dividing the number of bad blocks in the memory channel by the total number of memory blocks in the memory channel. The total BBR of the SSD is determined by summing together the BBRs of all of the memory channels as each of the memory channels are effectively coupled together, and a bad block in one memory channel causes a bad block in each of the other memory channels as illustrated in FIG. 6A.
For example, FIG. 6B is a block diagram of a conventional SSD having eight memory channels. Assuming that each memory channel has 100 blocks, then the BBR for the first channel, BBR0, is one percent as there is one bad block out of 100 total blocks, and the BBR for the second channel, BBR1, is two percent. The total BBR for the SSD, BBRtot, is ten percent, which is the sum of BBR0 through BBR7. This method of bad block management may create a greater total BBR, BBRtot, that is n times greater than a BBR of an individual memory channel. The higher the BBR an SSD has translates to a lower total storage capacity of the SSD as bad blocks are no longer used for data storage.
Accordingly, an improved solid-state memory architecture and bad block management method are desirable.